A Verification Framework for SoC FPGA Devices

A set of IP is proposed for in system verification for SoC FPGA devices. Currently this type of verification is done using a combination of existing JTAG based verification IP and block RAM resources on SoC FPGA devices. This alternative approach utilizes the ARM processor and native AMBA Bus FPGA interface to provide some of the debug functionality in the ARM. The primary advantage of this approach is the ability to continuously capture samples with a comparable amount of block RAM consumption. In addition, continuous data capture can be implemented without the overhead of tcl script interaction. The set of IP in this project has been developed to provide similar functionality offered by FPGA vendors. Resource utilization, latency, and throughput are used as comparative metrics. The IP consumes more resources than their JTAG and block RAM based counterparts in comparable configurations but provide a higher throughput and lower latency than standard verification tools.