Hardware Implementation of Hevc Inverse Transform

The High Efficiency Video Coding (HEVC) standard relies on the use of the inverse discrete cosine transform (IDCT) to perform video decompression. During encoding, the transform takes residual data and transforms it from the spatial domain to the frequency domain. This frequency domain representation can then be compressed, using quantization, while still retaining a high level of video quality when decoded and presented to the user. HEVC has increased the complexity of the decoder and the inverse transform lends itself well to hardware acceleration due to repeated addition and multiplication on unit blocks. With 4K video emerging as the successor to HD, hardware implementations will be critical to the performance of real time video applications. A hardware implementation of the inverse quantization and inverse transform, compliant to the HEVC standard, will be presented. The design targets the 4x4 inverse quantization and transform, synthesis, and place & route using the Nangate FreePDK45 Open Cell Library. An analysis of speed, area, and throughput will be presented and compared to similar ASIC designs. The operational frequency of this design will support 4K video at up to 30 frames/sec. The core area of this design takes up 14664 µm2 and can operate at max. frequency of 367 MHz.